? semiconductor components industries, llc, 2014 july, 2014 ? rev. 11 1 publication order number: mc14007ub/d mc14007ub dual complementary pair plus inverter the mc14007ub multipurpose device consists of three n?channel and three p?channel enhancement mode devices packaged to provide access to each device. these versatile parts are useful in inverter circuits, pulse?shapers, linear amplifiers, high input impedance amplifiers, threshold detectors, transmission gating, and functional gating. features ? diode protection on all inputs ? supply voltage range = 3.0 vdc to 18 vdc ? capable of driving two low?power ttl loads or one low?power schottky ttl load over the rated temperature range ? pin?for?pin replacement for cd4007a or cd4007ub ? this device has 2 outputs without esd protection. antistatic precautions must be taken. ? nlv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable ? this device is pb?free and is rohs compliant maximum ratings (voltages referenced to v ss ) symbol parameter value unit v dd dc supply voltage range ?0.5 to +18.0 v v in , v out input or output voltage range (dc or transient) ?0.5 to v dd +0.5 v i in , i out input or output current (dc or transient) per pin 10 ma p d power dissipation, per package (note 1) 500 mw t a ambient temperature range ?55 to +125 c t stg storage temperature range ?65 to +150 c t l lead temperature (8 second soldering) 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. temperature derating: ?d/dw? package: ?7.0 mw/ c from 65 c 5o 125 c. see detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. ordering information 11 12 13 14 8 9 10 5 4 3 2 1 7 6 gate c s?p c out c d?p a v dd d?n a s?n c s?n b gate b s?p b d?p b v ss gate a d?n b pin assignment d = drain s = source marking diagram soic?14 d suffix case 751a 1 14 14007ug awlyww a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g = pb?free indicator http://onsemi.com
mc14007ub http://onsemi.com 2 figure 1. typical application: 2?input analog multiplexer a b c input input a b c 12 1 3 5 9 2 4 11 10 14 v dd 6 7v ss 8 13 input 1 0 output condition a = c, b = open a = b, c = open substrates of p?channel devices internally connected to v dd ; substrates of n?channel devices internally connected to v ss . figure 2. schematic 14 13 2 1 11 12 6 78 3 4 510 9 v dd = pin 14 v ss = pin 7
mc14007ub http://onsemi.com 3 electrical characteristics (voltages referenced to v ss ) symbo l characteristic v dd vdc ?55 c 25 c 125 c unit min max min typ (note 2) max min max v ol output voltage ?0? leve l v in = v dd or 0 v in = 0 or v dd ?1? leve l 5.0 10 15 ? ? ? 0.05 0.05 0.05 ? ? ? 0 0 0 0.05 0.05 0.05 ? ? ? 0.05 0.05 0.05 vdc v oh 5.0 10 15 4.95 9.95 14.95 ? ? ? 4.95 9.95 14.95 5.0 10 15 ? ? ? 4.95 9.95 14.95 ? ? ? vdc v il input voltage ?0? leve l (v o = 4.5 vdc) (v o = 9.0 vdc) (v o = 13.5 vdc) (v o = 0.5 vdc) ?1? leve l (v o = 1.0 vdc) (v o = 1.5 vdc) 5.0 10 15 ? ? ? 1.0 2.0 2.5 ? ? ? 2.25 4.50 6.75 1.0 2.0 2.5 ? ? ? 1.0 2.0 2.5 vdc v ih 5.0 10 15 4.0 8.0 12.5 ? ? ? 4.0 8.0 12.5 2.75 5.50 8.25 ? ? ? 4.0 8.0 12.5 ? ? ? vdc i oh output drive current (v oh = 2.5 vdc) source (v oh = 4.6 vdc) (v oh = 9.5 vdc) (v oh = 13.5 vdc) (v ol = 0.4 vdc) sin k (v ol = 0.5 vdc) (v ol = 1.5 vdc) 5.0 5.0 10 15 ?3.0 ?0.64 ?1.6 ?4.2 ? ? ? ? ?2.4 ?0.51 ?1.3 ?3.4 ?5.0 ?1.0 ?2.5 ?10 ? ? ? ? ?1.7 ?0.36 ?0.9 ?2.4 ? ? ? ? madc i ol 5.0 10 15 0.64 1.6 4.2 ? ? ? 0.51 1.3 3.4 1.0 2.5 10 ? ? ? 0.36 0.9 2.4 ? ? ? madc i in input current 15 ? 0.1 ? 0.00001 0.1 ? 1.0 adc c in input capacitance (v in = 0) ? ? ? ? 5.0 7.5 ? ? pf i dd quiescent current (per package) 5.0 10 15 ? ? ? 0.25 0.5 1.0 ? ? ? 0.0005 0.0010 0.0015 0.25 0.5 1.0 ? ? ? 7.5 15 30 adc i t total supply current (notes 3 and 4) (dynamic plus quiescent, per gate) (c l = 50 pf) 5.0 10 15 i t = (0.7 a/khz) f + i dd /6 i t = (1.4 a/khz) f + i dd /6 i t = (2.2 a/khz) f + i dd /6 adc product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 2. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance. 3. the formulas given are for the typical characteristics only at 25 c. 4. to calculate total supply current at loads other than 50 pf: i t (c l ) = i t (50 pf) + (c l ? 50) vfk where: i t is in a (per package), c l in pf, v = (v dd ? v ss ) in volts, f in khz is input frequency, and k = 0.003.
mc14007ub http://onsemi.com 4 switching characteristics (note 5) (c l = 50 pf, t a = 25 c) symbol characteristic v dd vdc min typ (note 6) max unit t tlh output rise time t tlh = (1.2 ns/pf) c l + 30 ns t tlh = (0.5 ns/pf) c l + 20 ns t tlh = (0.4 ns/pf) c l + 15 ns 5.0 10 15 ? ? ? 90 45 35 180 90 70 ns t thl output fall time t thl = (1.2 ns/pf) c l + 15 ns t thl = (0.5 ns/pf) c l + 15 ns t thl = (0.4 ns/pf) c l + 10 ns 5.0 10 15 ? ? ? 75 40 30 150 80 60 ns t plh turn?off delay time t plh = (1.5 ns/pf) c l + 35 ns t plh = (0.2 ns/pf) c l + 20 ns t plh = (0.15 ns/pf) c l + 17.5 ns 5.0 10 15 ? ? ? 60 30 25 125 75 55 ns t phl turn?on delay time t phl = (1.0 ns/pf) c l + 10 ns t phl = (0.3 ns/pf) c l + 15 ns t phl = (0.2 ns/pf) c l + 15 ns 5.0 10 15 ? ? ? 60 30 25 125 75 55 ns 5. the formulas given are for the typical characteristics only. switching specifications are for device connected as an inverter . 6. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance. figure 3. typical output source characteristics figure 4. typical output sink characteristics v dd = -v gs v dd = v gs 14 14 v ds = v oh - v dd v ds = v ol v ss v ss 7 7 i oh i ol i oh , drain current (madc) i ol , drain current (madc) 0 -4.0 -8.0 -12 -16 -20 -8.0 -10 -6.0 -4.0 -2.0 -0 v ds , drain voltage (vdc) 20 16 12 8.0 4.0 0 0 2.0 4.0 6.0 8.0 10 v ds , drain voltage (vdc) t a = -55 c t a = +25 c t a = +125 c a b c v gs = -5.0 vdc b c a -10 vdc -15 vdc c b c b a a a b c a b c a b c 5.0 vdc t a = -55 c t a = +25 c t a = +125 c a b c v gs = 15 vdc 10 vdc all unused inputs connected to ground. all unused inputs connected to ground. these typical curves are not guarantees, but are design aids. caution: the maximum current rating is 10 ma per pin.
mc14007ub http://onsemi.com 5 figure 5. switching time and power dissipation test circuit and waveforms pulse generator v dd 500 f 0.01 f ceramic 14 c l v out v ss 7 v in i d v in v out 90% 50% 10% 90% 50% 10% 20 ns 20 ns v dd v ss v oh v ol t thl t tlh t phl t plh applications the mc14007ub dual pair plus inverter, which has access to all its elements offers a number of unique circuit applications. figures 1, 6, and 7 are a few examples of the device flexibility. figure 6. 3?state buffer +v dd disable3 input10 disable 6 12output 11 1 2 9 8 7 input disable output 1 0 x 0 0 1 0 1 open x = don?t care figure 7. aoi functions using tree logic v dd 14 13 11 10 3 6 b c a 9 5 4 8 7 1 2 output out = a+b ? c substrates of p?channel devices internally connected to v dd ; substrates of n?channel devices internally connected to v ss . 12
mc14007ub http://onsemi.com 6 ordering information device package shipping ? mc14007ubdg soic?14 (pb?free) 55 units / rail mc14007ubdr2g soic?14 (pb?free) 2500 / tape & reel NLV14007UBDR2G* soic?14 (pb?free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *nlv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable.
mc14007ub http://onsemi.com 7 package dimensions soic?14 nb case 751a?03 issue k notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of at maximum material condition. 4. dimensions d and e do not include mold protrusions. 5. maximum mold protrusion 0.15 per side. h 14 8 7 1 m 0.25 b m c h x 45 seating plane a1 a m s a m 0.25 b s c b 13x b a e d e detail a l a3 detail a dim min max min max inches millimeters d 8.55 8.75 0.337 0.344 e 3.80 4.00 0.150 0.157 a 1.35 1.75 0.054 0.068 b 0.35 0.49 0.014 0.019 l 0.40 1.25 0.016 0.049 e 1.27 bsc 0.050 bsc a3 0.19 0.25 0.008 0.010 a1 0.10 0.25 0.004 0.010 m 0 7 0 7 h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.019 6.50 14x 0.58 14x 1.18 1.27 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemni fy and hold scillc and its officers, em ployees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 mc14007ub/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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